Semiconductor integrated circuits are fabricated with multiple layers, some of them patterned, of semiconductive, insulating, and conductive materials, as well as additional layers providing functions such as bonding, a migration barrier, and an ohmic contacts. Thin films of these various materials are deposited or formed in a number of ways, the most important of which in modem processing are physical vapor deposition (PVD), also known as sputtering, and chemical vapor deposition (CVD).
In CVD, a substrate, for example, a silicon wafer, which may already have patterned layers of silicon or other materials formed thereon, is exposed to a precursor gas which reacts at the surface of the substrate and deposits a product of the reaction on the substrate to thereby grow a film thereon. A simple example includes the use of silane (SiH.sub.4) to deposit silicon with the hydrogen forming a gaseous byproduct which is evacuated from the chamber. However, the present application is directed more to CVD of a conductive material such as TiN.
This surface reaction can be activated in at least two different ways. In a thermal process, the substrate is heated to a sufficiently high temperature to provide the activation energy for molecules of the precursor gas adjacent to the substrate to react there and deposit a layer upon the substrate. In a plasma-enhanced CVD process (PECVD), the precursor gas is subjected to a sufficiently high field that it forms a plasma. As a result the precursor gas is excited into energetic states, such as ions or radicals, which readily react on the substrate surface to form the desired layered material.
Zhao et al. describe an example of a CVD deposition chamber in U.S. patent application Ser. No. 08/348,273 filed on Nov. 30, 1994, now U.S. Pat. No. 5,558,717, expressly incorporated herein by reference, and which is assigned to a common assignee. This type of CVD chamber is available from Applied Materials, Inc. of Santa Clara, Calif. as the CVD DxZ chamber.
As described in this patent and as illustrated in the cross sectional side view of FIG. 1, a CVD reactor chamber 30 includes a pedestal 32 supporting on a supporting surface 34 a wafer 36 to be deposited by CVD with a layer of material. Lift pins 38 are slidable within the pedestal 32 but are kept from falling out by conical heads on their upper ends. The lower ends of the lift pins 38 are engageable with a vertically movable lifting ring 39 and thus can be lifted above the pedestal's surface 34. The pedestal 32 is also vertically movable, and in cooperation with the lift pins 38 and the lifting ring 39, an unillustrated robot blade transfers a wafer into chamber 30, the lift pins 38 raise the wafer 36 off the robot blade, and then the pedestal 32 rises to raise the wafer 36 off the lift pins 38 and onto its supporting surface 34.
The pedestal 32 then further raises the wafer 36 into close opposition to a gas distribution faceplate 40, often referred to as a showerhead, which includes a large number of passageways 42 for jetting the process gas to the opposed wafer 36. That is, the passageways 42 guide the process gas into a processing space 56 towards the wafer 36. The process gas is injected into the reactor chamber 30 through a central gas inlet 44 in a gas-feed cover plate 46 to a first disk-shaped manifold 48 and from thence through passageways 50 in a baffle plate 52 to a second disk-shaped manifold 54 in back of the showerhead 40.
As indicated by the arrows, the process gas jets from the holes 42 in the showerhead 40 into the processing space 56 between the showerhead 40 and pedestal 32 so as to react at the surface of the closely spaced wafer 36. Unreacted process gas and reaction byproducts flow radially outwardly to an annular pumping channel 60 surrounding the upper periphery of the pedestal 32. The pumping channel 60 is generally closed but on the receiving end includes an annular choke aperture 62 between the pumping channel 60 and the processing space 56 over the wafer 36. The choke aperture 62 is formed between an isolator 64, to be described later, set in a lid rim 66 and an insulating annular chamber insert 68 resting on a ledge 70 on the inside of the main chamber body 72. The choke aperture 62 is formed between the main chamber and a removable lid attached to the chamber so that a fully annular choke aperture 62 can be achieved. The choke aperture 62 has a substantially smaller width than the depth of the processing space 56 between the showerhead 40 and the wafer 36 and is substantially smaller than the minimum lateral dimensions of the circumferential pumping channel 60, for example by at least a factor of five. The width of the choke aperture 62 is made small enough and its length long enough so as to create sufficient aerodynamic resistance at the operating pressure and gas flow so that the pressure drop across the choke aperture 62 is substantially larger than any pressure drops across the radius of the wafer 36 or around the circumference of the annular pumping channel 60. In practice, it is not untypical that the choke aperture 62 introduces enough aerodynamic impedance that the pressure drop from the middle of the wafer 36 to within the pumping channel 60 is no more than 10% of the circumferential pressure drop within the pumping channel 60.
The pumping channel 60 is connected through a constricted exhaust aperture 74 to a pumping plenum 76, and a valve 78 gates the exhaust through an exhaust vent 80 to a vacuum pump 82. The constricted exhaust aperture 74 performs a function similar to that of the choke aperture 62 in introducing an aerodynamic impedance such that the pressure within the pump channel 60 is substantially constant.
The restricted choke and exhaust apertures 62, 74 create a nearly uniform pressure around the circumferential pumping channel 60. The resultant gas distribution flow pattern across the wafer 36 is shown in arrowed lines 84 in FIG. 2. The process gas and its reaction byproducts flow from the center of the showerhead 40 across the wafer 36 and the periphery of the pedestal 32 along radial paths 84 and then through the choke aperture 62 to the pumping channel 60. The gas then flows circumferentially along paths 86 in the pumping channel 60 to the exhaust aperture 74 and then through the exhaust plenum 76 and the exhaust vent 80 to the vacuum pump 82. Because of the restrictions 62, 74, the radial flow 84 across the wafer 36 is nearly uniform in the azimuthal direction.
As shown in FIGS. 1 and 3 (FIG. 3 being a closeup view of the upper right corner of FIG. 1), the ledge 70 in the chamber body 72 supports the chamber shield liner 68, which forms the bottom of the pumping channel 60. The chamber lid rim 66 forms the top and part of the outside wall of the pumping channel 60 along with part of the chamber body 72. The inside upper edge of the pumping channel 60 is formed by the isolator ring 64, which is made of a ceramic or other electrically insulating material which insulates the metallic showerhead 40 from the chamber body 72.
The CVD reactor chamber 30 of FIG. 1 can be operated in two modes, thermal and plasma-enhanced. In the thermal mode, an electrical power source 90 supplies power to a resistive heater 92 at the top of the pedestal 32 to thereby heat the pedestal 32 and thus the wafer 36 to an elevated temperature sufficient to thermally activate the CVD deposition reaction. In the plasma-enhanced mode, an RF electrical source 94 is passed by a switch 96 to the metallic showerhead 40, which thus acts as an electrode. The showerhead 40 is electrically insulated from the lid rim 66 and the main chamber body 72 by the annular isolator ring 64, typically formed of an electrically non-conductive ceramic. The pedestal 32 is connected to a biasing element 98 associated with the RF source 94 so that RF power is split between the showerhead 40 and the pedestal 32. Sufficient voltage and power is applied by the RF source 94 to cause the process gas in the processing space 56 between the showerhead 40 and the pedestal 32 to discharge and to form a plasma.
Only recently has it been attempted to use this general type of CVD reactor to deposit a film of a conductive material, such as titanium nitride (TiN), using the thermal TDMAT process described by Sandhu et al. in U.S. patent application, Ser. No. 07/898,059. A related plasma process is described by Sandhu et al. in U.S. Pat. No. 5,246,881. The deposition of a conductive material in this chamber has presented some problems that are addressed by this invention.
Titanium nitride is a moderately good electrical conductor, but in semiconductor processing it is used primarily to function as a barrier layer and to assist titanium as a glue layer. This process is often applied to the contact structure illustrated in the cross-sectional view of FIG. 4 in which an oxide layer 100, typically SiO.sub.2, is deposited to a thickness of about 1 .mu.m over a substrate 102 having a surface of crystalline silicon or polysilicon. The oxide layer 100 acts as an inter-level dielectric, but to provide electrical contact between levels a contact hole 104 is etched through the oxide layer 100 to be filled with a metal such as aluminum. However, in advanced integrated circuits, the contact hole 104 is narrow, often less than 0.35 .mu.m, and has an aspect ratio of 3 or more. Filling such a hole is difficult, but a somewhat standard process has been developed in which the hole 104 is first conformally coated with a titanium layer 106, and the titanium layer 106 is then conformally coated with a titanium nitride layer 108. Thereafter, an aluminum layer 110 is deposited, usually by physical vapor deposition, to fill the contact hole 104 and to provide electrical interconnection lines on the upper level. The Ti layer 106 provides a glue layer to both the underlying silicon and the oxide on the sidewalls. Also, it can be silicided with the underlying silicon to form an ohmic contact. The TiN layer 108 bonds well to the Ti layer 106, and the aluminum layer 110 wets well to the TiN so that the aluminum can better fill the contact hole 104 without forming an included void. Also, the TiN layer 108 acts as a barrier to prevent the aluminum 110 from migrating into the silicon substrate 102 and affecting its conductivity. In a via structure in which the substrate 102 includes an aluminum surface feature, the Ti layer 106 may not be needed. Even though the electrical conductivities of titanium and titanium nitride are not nearly as high as that of aluminum, they are sufficiently conductive in thin layers to provide a good electrical contact.
Titanium and titanium nitride can be deposited by either CVD or PVD, but CVD enjoys the advantage of more easily forming conformal layers in a hole having a high aspect ratio. The thermal TDMAT process is such a CVD process for conformally coating TiN in a narrow hole.
In the TDMAT process, a precursor gas of tetrakis-dimethylamido-titanium, Ti(N(CH.sub.4).sub.2).sub.4, is injected into the chamber through the showerhead 40 at a pressure of about 1 to 9 Torr while the pedestal 32 holds the substrate 36 at an elevated temperature of about 360.degree. C. or higher. Thereby, a conductive and conformal TiN layer is deposited on the substrate 36 in a CVD process. The TDMAT process is a thermal process not usually relying upon plasma excitation of the precursor gas.
However, it has been found that the TiN layer initially formed by the TDMAT process includes an excessive amount of carbon in the form of included polymers which degrade its conductivity. Thus, the TDMAT deposition is usually followed by a second step of plasma treating the deposited TiN layer. The TDMAT gas in the chamber is replaced by a gas mixture of H.sub.2 and N.sub.2 in about a 50:50 ratio at a pressure of 0.5 to 10 Torr, and the RF power source 94 is switched on to create electric fields between the showerhead 40 and the pedestal 32 sufficient to discharge the H.sub.2 :N.sub.2 gas to form a plasma. The hydrogen and nitrogen species in the plasma reduce the carbonaceous polymer to volatile byproducts which are exhausted from the system. The plasma treatment thereby removes the carbon to improve the quality of the TiN film.
The plasma treatment process, when performed in the same chamber as the thermal CVD deposition, has demonstrated some problems with uniformity and reproducibility. We believe that the problems originate from extraneous metal depositions on reactor surfaces affecting the plasma and producing excess particles within the chamber. We also believe that the depositions occur in two different areas, an area at the top of the pedestal 32 outside of the wafer 36 and an area in and around the pumping channel 60.
A first problem, we believe, relates to extraneous metal deposition on the pedestal 32 because exposed portions of the pedestal 32 are at a temperature equal to and often much greater than that of the wafer 36. As shown in the cross-sectional view of FIG. 3, the portion of the pedestal 32 which extends beyond the outside edge of the wafer 36 is subject to a buildup 120 of deposited material from the following mechanism.
During the thermal phase of the TDMAT process during which the conductive TiN is deposited, the heater 92, shown in FIG. 1, installed in the pedestal 32 heats the pedestal 32, and the heat is transferred thence to the wafer 36. There are several reasons why the exposed portion of the pedestal 32 tends to be at a significantly higher temperature than that of the wafer 36. The showerhead 40 operates at a much lower temperature, typically around 100.degree. C. to readily sink heat from opposed elements. On the other hand, the wafer 36 is incompletely heat sunk on the pedestal 32 and transmits heat conducted to it from the pedestal 32 more poorly than does the directly radiating and more highly thermally conductive pedestal 32. Also, since the chamber is also used for the low-temperature plasma treating phase and additional time is consumed transferring wafers into and out of the chamber, the duty cycle for the high-temperature operation is relatively low and it is necessary to heat the wafer 36 to the required high processing temperatures. To quickly raise the temperature of the wafer 36 to its processing temperature, the temperature of the pedestal 32 is raised to a higher temperature than that of the wafer 36. For all these reasons, the processing temperature of the wafer 36 may be set to 360.degree. C. while the exposed portion of the pedestal tends to be at a significantly higher temperature of 425.degree. C.
Since the rate of deposition on a surface is proportional to the temperature of the surface (the higher the temperature the more rapid the deposition), the higher temperature of the exposed outer edge of the pedestal 32 causes, as illustrated in FIG. 3, a rapid buildup 120 of deposited film. As the thickness of the deposited film increases over the processing cycles of many wafers, deleterious effects may occur. The buildup of film thickness at the edge may create an artificial perimeter rim which prevents the wafer 36 from being in full contact with the surface of the pedestal 32, as required for efficient processing. Similarly, once the buildup 120 has developed past some film thickness of the film, successively deposited film layers do not completely adhere to the underlying layers. Portions of the film can then form particles or flakes that separate from the pedestal and float onto the wafer 36 being processed. The particles can create defects on the processed wafer.
A second problem related to extraneous metal deposition arises in that the conductive TiN film is also deposited, to a lesser extent because of lower surface temperatures, on other surfaces exposed to the process gas along its path from the showerhead 40 to and through the pumping channel 60 on its way to the chamber vacuum system 82. FIG. 5 shows an example of the buildup of a metal film 124 over and around the isolator ring 64 that can cause an electrical short between the electrically biased showerhead 40 and the grounded lid rim 66. FIG. 5 shows only an exaggerated film buildup 124 on the upper surface of the chamber. In reality, the film builds up on all surfaces, but the other buildup is not shown for clarity.
Another example of extraneous film deposition illustrated in FIG. 6 is the buildup of a conductive film 128 over the insulating alumina chamber insert 68 to the point that it extends across the pumping channel 60 and contacts the electrically grounded main chamber body 72. This extraneous deposition 128 thus extends the ground potential associated with the chamber body 72 and the lid rim 66 to the inner, upper edge of the insulating annular insert 68 closely adjacent the upper peripheral edge of the pedestal 32. The location and quality of plasma in the processing space 56 depends on the distance between the powered plasma source electrodes and surrounding surfaces and the difference between their respective electrical potentials. When, during a long process run, the chamber insert 68 effectively changes from being disposed as a insulator between the chamber body 72 and the plasma to being a grounded conductor, the location and quality of the plasma will be affected, particularly around the edges of the wafer 36. The distortion of the plasma due to the proximity of a closely adjacent electrical ground causes non-uniformity in the plasma, which affects the thickness of the film deposition and its surface properties.
During plasma processing, variations in uniformity of the plasma will affect the surface uniformity of the film produced. Therefore, variations in the intensity of the plasma will affect the uniformity of film properties. The conductivity, which is the inverse of the insulating quality, of the insulating members surrounding the location of the plasma changes as a conductive film is formed on their surfaces and as the conductive film forms a conductive path to adjacent conductive elements at different potentials. This variation in the conductive quality of the ostensibly insulating elements causes variations in the plasma which reduce the process repeatability.
A third problem related to extraneous metal deposition arises in that some electrically floating elements which are exposed to the plasma will accumulate a charge from the plasma. In the instance where these charged pieces are close to a grounded or electrically powered part, there is always a chance of arcing between the floating part and a ground or the electrode. In the instance when the wafer is supported on the pedestal, the wafer may act as a floating element which can become charged to cause arcing. Arcing creates particles and defects in the substrate. Therefore arcing to the wafer should be avoided and the uniformity of the envelope for the plasma treating the surface of the substrate should be held as uniform as possible.
To avoid these potentially deleterious effects, it is common practice to schedule a cleaning or maintenance cycle involving removal and replacement or cleaning of the pedestal before buildup of film can create undesired effects. However, this remedy is disadvantageous. Not only are pedestals expensive, but their replacement or cleaning involves a shut down of expensive equipment and additional operator time.
The buildup of unwanted film thickness on either the perimeter of the susceptor or across insulating members in the chamber requires they be periodically cleaned to prevent short-circuiting or unacceptable variations in the plasma treatment. The buildup of a thickness of an unwanted film creates a risk of short-circuiting by causing variations in the intensity and location of the electrical fields exciting the gas to a plasma state. Also, when the risk of conduction or arcing becomes high, a cleaning or maintenance cycle is initiated to restore the original distribution of the electrical field. Other consumable or maintainable components also require replacement or cleaning at certain intervals. Presently the risk of conductance and arcing sets the cleaning/maintenance interval. The mean number of wafers between cleans could be increased dramatically if the problem of film thickness adherence and conductivity across insulating members to grounded members, as described above, could be reduced or eliminated.
A CVD chamber, schematically illustrated in FIG. 7, is similar to that of FIG. 1 except that it is radiantly, not resistively, heated. It has been applied to the deposition of conductive materials and where plasma treatment of one sort or another was performed in the chamber. In this chamber, an argon treatment sputtering gas was energized into a plasma 130 between a pedestal electrode 132 and a counter electrode 134. An RF power source 136 provided RF power to energize the plasma. It was found, however, that, if the plasma was to be well confined in the processing space above the wafer, it was necessary to feed the RF power to a matching network 138 that selectably split the power between the pedestal electrode 132 and the counter electrode 134. It is believed that thus splitting the RF power better confines the plasma because the plasma with a grounded electrode tends to spread outside of the area of the wafer and to be more affected by the extraneously deposited metal layers described above. The matching network 138 allowed the RF power split to the pedestal electrode 132 to be the fraction of 30%, 50%, or 70% of the total power.
It is desired that CVD chambers of the type shown in FIG. 1, which were designed for deposition of dielectrics, be adapted to allow them to deposit metallic materials.
Therefore, it is desired that this chamber be improved to alleviate the problems of plasma instability and arcing. It is further desired that the frequency for routine maintenance and cleaning be reduced.